1. Field of the Invention
The present invention relates to a semiconductor testing jig that holds a plurality of vertical semiconductor devices each having a lower surface electrode and an upper surface electrode in a state of being in contact with a mounting surface and to a transfer jig for the semiconductor testing jig.
2. Description of the Background Art
When a test on electrical properties of individual semiconductor devices formed into chips is carried out, it is common to carry out the test on the electrical properties individually by bringing a measuring electrode into contact with the semiconductor devices after positioning the semiconductor devices individually. Thus, workability is poor, and the number of testing processes tends to increase.
To solve the problems, a semiconductor transfer tray capable of collectively handling a plurality of semiconductor devices such as IC packages and an inspection apparatus for testing have been developed (for example, see Japanese Patent Application Laid-Open No. 2006-292727).
In a semiconductor device having a vertical structure that passes a current in a vertical direction, namely, an out-of-plane direction of the semiconductor device (hereinafter, referred to as a “vertical semiconductor device”), a stage on the inspection apparatus for testing side fixing a mounting surface of the vertical semiconductor device is one of the measuring electrodes. Consequently, adhesion of the stage to the semiconductor device affects a contact resistance, thereby affecting the electrical properties of the semiconductor device.
If there is a foreign matter such as a dust on the stage, the vertical semiconductor device is disposed on the foreign matter, and when the measuring electrode comes in contact with the vertical semiconductor device, the mounting surface of the vertical semiconductor device is pressed hard against the foreign matter. If the foreign matter is large, a defect such as a crack is generated in a contact portion of the vertical semiconductor device with the stage and in a portion near the contact portion, resulting in a breakage in a part of the vertical semiconductor device. The broken vertical semiconductor device is counted as a defective product.
On the other hand, if the foreign matter is not large enough to be visually checked and if the foreign matter is relatively small in the size of, for example, several tens of μm or less, pressure applied to bring the measuring electrode into contact with the vertical semiconductor device leads to distortion of the vertical semiconductor device. Thus, leakage of current due to piezo electric effect increases, and thus the vertical semiconductor device is counted as a defective product.
As a measure against an increase in a defective rate of the vertical semiconductor device due to the foreign matter on the stage, the method for adding a stress buffer film to a back side of a semiconductor substrate to reduce the stress due to the foreign matter has been developed (for example, see Japanese Patent Application Laid-Open No. 2008-4739).
It is known that when a semiconductor wafer is formed into small pieces, many small flakes or chippings of a semiconductor wafer material are generated from a side surface of the semiconductor device and become foreign matters adhering to the side surface and close to the side surface, which are subsequently brought into a testing process. The adhesion of the foreign matters may also cause an electro static charge generated during the process. In addition, it is known that a metal caught during the manufacturing process causes to generate a foreign matter. Moreover, it is known that a fragment generated by dice-cutting becomes a foreign matter when the fragment connected to a metal electrode film is brought into a next process.
As a measure against a foreign matter which is a fragment generated by dice-cutting and connected to the metal electrode film, the method for removing the metal electrode film on a scribe line has been developed (for example, see Japanese Patent Application Laid-Open No. 2008-141135).
However, the semiconductor transfer tray and the inspection apparatus for testing disclosed in Japanese Patent Application Laid-Open No. 2006-292727 have complex structures and cannot be compatible with the vertical semiconductor device. Moreover, the semiconductor transfer tray and the inspection apparatus for testing are not subjected to the measure against a foreign matter.
In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2008-4739, a film that reduces stress due to a foreign matter put on semiconductor substrates is added to all the semiconductor substrates for measuring electrical properties, to thereby achieve a reduction in a defective rate. However, the film needs to be added to all the semiconductor substrates, and thus the number of processes for manufacturing the semiconductor device increases. Moreover, the addition of the film increases manufacturing costs of the semiconductor device.
In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2008-141135, removing the metal electrode film from the scribe line suppresses the generation of the foreign matter. However, the metal electrode film needs to be removed from every semiconductor wafer, and thus the number of processes for manufacturing the semiconductor device increases. Moreover, upon removal of the metal electrode film, an adhesive tape is attached to every semiconductor wafer and then peeled off again, so that the addition of the adhesive tape increases manufacturing costs of the semiconductor device.